In recent years, the market has demanded reduced power consumption of semiconductor circuits in order to increase battery duration in mobile devices and to reduce the costs of heat dissipation parts of semiconductor devices. To reduce the power consumption of semiconductor circuits, it is desirable for semiconductor circuits to be operated at as low a power supply voltage as possible. For example, in a semiconductor circuit including a processor core and a peripheral circuit, different power supply voltages may be supplied to the processor core and the peripheral circuit. For example, 1.2 V may be supplied to the processor core, and 0.8 V may be supplied to the peripheral circuit. Generally, the output of a voltage regulator circuit is used as a power supply to be supplied to each circuit.
The output voltage of the voltage regulator circuit is preferably independent of the output current. For example, even when the current consumed by the processor core changes from 0 A to 1 A, it is preferable that the output voltage of the voltage regulator circuit remains at 1.2 V. However, the output voltage of the voltage regulator circuit generates a potential difference by using an output transistor resistance component, and it takes certain time to perform control thereof. A voltage drop occurs due to the resistance component when the output current suddenly increases in an amount of time shorter than the control time, resulting in drop of the output voltage. Because voltage drop causes the semiconductor circuit to malfunction, it is desired to avoid such voltage drop.
FIG. 1A is a diagram illustrating an example of a voltage regulator circuit. FIG. 1B is a timing chart illustrating the operation of the voltage regulator circuit (e.g., see the specification of U.S. Pat. No. 4,952,863). The voltage regulator circuit includes a differential amplifier 10, a driver circuit 12, a delay circuit 14, a monostable multivibrator circuit 16, transistors T6 and T11 to T13, and a capacitor CL. The differential amplifier 10 includes transistors T1 to T5. The driver circuit 12 includes transistors T7 to T10.
To suppress a drop of an output voltage Vout in response to a sudden increase in the output current, the voltage regulator circuit suddenly reduces the resistance of the output transistor T6 using a signal obtained by causing an input signal Vin of the driver circuit 12, which is a voltage supply destination, to go through the monostable multivibrator circuit 16. As illustrated in FIG. 1B, a pulse for a certain period is generated at node E in response to a rising edge of the input signal Vin, and the n-channel output transistor T6 is turned ON typically during that period in which the pulse is being generated. The output voltage Vout is supplied as a power supply voltage of the driver circuit 12. Without the transistor T13, after time t1, the output current suddenly increases, and the output voltage Vout decreases (broken line). The transistor T13 has the effect of suppressing drop of the output voltage Vout (solid line).
The technique for controlling a dummy load in accordance with the operation mode of a circuit is known (e.g., see Japanese Unexamined Patent Application Publication No. 2005-310060). This technique performs control so that an output current value does not suddenly increase by gradually changing the magnitude of the dummy load when the circuit changes from a sleep state to an active state.
Most of the current consumed by the processor core is consumed by a clock signal. The current consumption increases most when the state changes from a state where the input clock signal is stopped to a state where the input clock signal is activated. Activation of the clock signal corresponds to a state where a repetitive pulse signal is input to the clock signal.
FIG. 2 is a timing chart illustrating the operation when the clock signal is input as the input signal Vin to the voltage regulator circuit illustrated in FIG. 1A. In this operation, it is assumed that the clock signal is input as the input signal Vin. While the clock signal Vin is being supplied, the output voltage Vout always increases up to a power supply voltage Vcc, and a desired minimum voltage level may not be maintained. Therefore, the voltage regulator circuit uselessly consumes power.
It takes time for the voltage regulator circuit to gradually change the dummy load when the method described in Japanese Unexamined Patent Application Publication No. 2005-310060 is used. A processor circuit that promptly consumes current after the clock signal is input might not cope with an increase in current.